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PRELIMINARY DATA SHEET
MICRONAS
UAC 3552A Universal Serial Bus DAC
Edition Nov. 9, 1999 6251-487-1PD
MICRONAS
UAC 3552A
Contents Page 4 5 6 6 6 6 6 6 6 6 6 6 7 8 8 8 9 9 9 10 10 10 10 10 10 10 10 10 10 11 11 11 11 12 12 13 13 13 13 13 Section 1. 1.1. 2. 2.1. 2.1.1. 2.1.1.1. 2.1.1.2. 2.1.1.3. 2.1.2. 2.1.3. 2.1.4. 2.1.5. 2.1.5.1. 2.1.5.2. 2.1.5.3. 2.1.5.4. 2.1.5.5. 2.1.5.6. 2.1.6. 2.1.7. 2.1.7.1. 2.1.7.2. 2.1.7.3. 2.1.8. 2.2. 2.2.1. 2.2.1.1. 2.2.1.2. 2.2.1.3. 2.2.1.4. 2.2.2. 2.2.2.1. 2.2.2.2. 2.2.2.3. 2.2.2.4. 2.2.2.5. 2.2.2.6. 2.2.2.7. 2.2.3. 2.2.3.1. Title Introduction Features Functional Description Hardware USB Interface Transceiver Interface Engine Microcontroller Audio Control Interface Audio Streaming Interface Audio Processing Unit Analog Back-end DAC Analog Low-pass Postfilter Op Amps Input Mixer Analog Volume Control Line-out/Headphone Amplifier General Purpose I/O Special I/O SOF (Start of Frame) AUXEN SUSPEND Clock System Software USB Microcontroller Software Chapter 9 Functions Device Descriptor String Descriptor HID Report Descriptor Audio Processing Software Sample Rate Converter Automatic Gain Control Bass Control Treble Control Bass Boost Control Parametric Equalizer Volume and Balance Control Mute Control Oversampling
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Contents, continued Page 14 14 14 16 16 16 17 17 18 19 19 20 22 26 26 27 28 Section 3. 3.1. 3.2. 3.3. 3.3.1. 3.3.2. 3.3.3. 3.4. 3.5. 3.6. 3.6.1. 3.6.2. 3.6.3. 4. 4.1. 4.2. 5. Title Specifications Outline Dimensions Pin Connections and Short Descriptions Pin Descriptions Power Supply Pins Analog Audio Pins Other Pins Pin Configuration Pin Circuits Electrical Characteristics Absolute Maximum Ratings Recommended Operating Conditions Characteristics Applications Recommended Low-Pass Filters for Analog Outputs Typical Application Data Sheet History
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Universal Serial Bus DAC 1. Introduction The UAC 3552A is the first member of Micronas' USB audio controller family of ICs targeting a wide variety of audio applications on the USB. The UAC 3552A is a single-chip, high-precision digital-to-analog audio converter. It includes a high-quality audio sample rate converter and is able to support a wide range of sample rates, as well as different audio formats. The IC contains a complete USB transceiver that allows direct connection to the USB. An on-chip EEPROM allows storing of manufacturer-specific data or product identification. The EEPROM can be programmed directly via the USB. Baseband audio processing is handled by an internal, powerful DSP. Apart from basic audio features, like tone and volume control, there is enough processing power left to realize customer-specific applications.
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The audio DAC uses Micronas' proprietary multibit sigma-delta technique. It features very low sensitivity to clock jitter, high linearity, and a superior S/N ratio. The UAC 3552A provides an on-chip headphone/ speaker amplifier. Moreover, mixing additional analog audio sources to the D/A-converted signal is supported. The IC is designed for all kinds of USB audio applications, such as USB active speakers, USB headphones, and USB interfaces to home stereo equipment, etc. Any existing analog speaker set can easily be upgraded to USB by just including the UAC 3552A according to the application circuit on page 27. No software development is required, because all drivers are already part of the operating system which supports USB (e. g. WindowsTM 98).
HID IO
Analog Input
External Loop-through Filter
EEPROM
D+ USB Interface D- DSP DAC
Input Select and Mixing
Volume and Headphone Amplifier
OUTL OUTR
ROM
ROM
+5 V GND Fig. 1-1: Block diagram of the UAC 3552A
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1.1. Features - single-chip, USB specification 1.0/1.1 compliant, stereo audio D/A converter - 12-Mbit/s USB transceiver - adaptive isochronous endpoint for USB Audio - USB-programmable vendor IDs (1024-bit EEPROM on chip) - four general purpose input pins and four output pins (human interface pins) - customizable I/O functionality by download-software - supports 16-bit mono/stereo and 24-bit stereo audio data - adaptive sample rate converter for 5 to 50 kHz input sampling rate - audio baseband control: bass, treble, volume, and balance, additional analog volume, mute - bass boost - automatic gain control (AGC) - "PerfectSpeaker" digital speaker equalizer - THD better than 0.01 %, SNR of 96 dB - integrated low-power stereo headphone amplifier - on-chip op amps for external analog filter - analog stereo input (AUX) with source selection and mixing - single 5-V power supply
Active Stereo Speakers
USB UAC Headphones
Stereo Equipment Fig. 1-2: System application diagram
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2. Functional Description 2.1. Hardware A detailed block diagram of the UAC 3552A is depicted in Fig. 2-1. The functions of the blocks are explained in the following sections.
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The ROM contains the USB drivers for the microcontroller as well as the complete descriptor table including the report descriptor for the HID-class. Some parts of the descriptor which are subjected to be changed by the customer, however, reside in the EEPROM. The EEPROM is built to keep static customer-related data that will customize the UAC 3552A-based USB device during production. The 128x8 bit EEPROM contains the customer specific information of the USB device descriptor, like vendor ID, product ID, as well as strings for manufacturer, product and serial number. Apart from this USBrelated information, the EEPROM holds customer-specific parameters for the PerfectSpeaker equalizer. The UAC 3552A is shipped with a preprogrammed EEPROM that allows normal USB functionality even if no reprogramming is performed on the customer's side. The EEPROM can be programmed via USB by means of UAC 3552A application tools.
2.1.1. USB Interface 2.1.1.1. Transceiver The differential input receiver is used to accept the USB data signal according to the full-speed (12 MB/s) USB driver characteristics (USB SPEC 1.1 - 7.1.4).
2.1.1.2. Interface Engine The interface engine comprises two major sections: the transceiver logic and the receiver logic. The transceiver logic transmits data packets built in memory by the microcontroller. These packets are converted from a serial to a parallel data stream. This includes NRZI encoding, bit stuffing, CRC-computation, and addition of SYNC field and EOP. The receiver logic will receive USB data and stores these packets in its memory for processing by the microcontroller. Serial USB data is converted to a byte-wide parallel data stream and stored in system memory. In addition to USB basic data decoding, the Rx logic performs a PID check and protocol layer checks.
2.1.2. Audio Control Interface The audio control interface links the microcontroller to the DSP and is used to initialize the DSP and to transmit audio-related USB control data, like volume setting, tone control etc.
2.1.3. Audio Streaming Interface 2.1.1.3. Microcontroller The microcontroller manages buffers for all enabled endpoints and interacts with the interface engine. The buffers are built and decoded in memory. This way, the microcontroller realizes the USB protocol handling, like USB reset, enumeration, and all chapter 9 processing, error handling, as well as class-specific endpoint handling, like audio class and HID class. The audio-class processing consists of interpreting the USB audio commands and accordingly controlling the DSP-audio function through a dedicated audio-control-interface to the DSP. HID class processing means polling keys providing the corresponding key-codes to the host-computer's requests. These keys are connected to the GPIO-pins. The RAM can be accessed by the microcontroller and by the interface-engine's DMA-controller. All endpoint communication is realized with intelligent buffer management built up in the RAM. A part of the RAM is reserved for download software. This allows adding extra functionality to the GPIO pins, like I2C-handling or any other control of external components via USB. Downloading is handled by an extra driver which allows direct RAM/ROM access via USB. The audio streaming interface directly connects the serial interface engine to the DSP in order to transmit the digital audio data. The interface collects and buffers the burst audio data for further processing by the audio processing unit.
2.1.4. Audio Processing Unit The audio processing unit is a powerful DSP core which allows high-quality sample conversion, baseband audio processing, and interpolation filtering used for oversampling DAC, as well as customized algorithms. For more details on the software see Section 2.2.2. "Audio Processing Software" on page 11.
2.1.5. Analog Back-end The analog back-end comprises the audio DAC, analog filters, input mixer, op amps for optimal external postfiltering, analog volume and mute, and the output amplifier.
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2.1.5.1. DAC The DAC uses oversampling technique with 3rd-order multibit noise-shaping. This technique results in extremely low quantization noise in the audio band.
DMINUS 24 DPLUS 25 26 VREG
Transceiver
Interface Engine
RAM
C
14 15 16 17 19 20 21 22 29 30 31 32 33 GPIO0 GPIO1 GPIO2 GPIO3 GPIO4 GPIO5 GPIO6 GPIO7 TEST RESQ SUSPEND SOF AUXEN
ROM
GP I/O
XTI
8
Oscillator
XTO 9
EEPROM
Control I/O
Audio Streaming Interface
Audio Control Interface
Audio Processing Unit
DAC Digital Supply
AUXL AUXR 36 37
27 28
VDD VSS
Analog Input
Input Mixer
6 AVDD0 AVDD1 AVSS0 AVSS1 VREF AGNDC
Volume Analog Supply Headphone Amplifier
4 OUTL 5 OUTR
7 3 2 44 1
Fig. 2-1: Detailed block diagram of the UAC 3552A
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2.1.5.2. Analog Low-pass The output of the DAC is filterted by an analog lowpass filter with a cut-off frequency of approximately 1.4 MHz. This filter removes the high-frequency components of the noise-shaping signal. Table 2-1: AUXEN pin AUXEN 0 1 2.1.5.3. Postfilter Op Amps This block contains the active components for the optional analog postfilters. It is recommended to use a second-order filter (see Section 4. "Applications" on page 26) in order to attenuate the out-of-band noise caused by the noise shaper The op amps and all I/Opins for this block are shown in Fig. 2-2.
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AUX not selected AUX selected
This allows to use a jack that switches the AUXEN to low when an analog source is plugged in, according to the application note Section 4. "Applications" on page 26. The DAC-signal is permanently connected to the mixer because the DAC is extremely quiet if no USB audio is applied. The AUXEN pin also keeps the UAC 3552A from entering the low-power mode when an analog source is connected. Please note that in this mode, the UAC 3552A is not USB-compliant. If the USB is not connected the GPIO pins work as an USB-independent volume control (see Table 2-2). BassBoost is not supported in this mode.
2.1.5.4. Input Mixer This block is used to mix the auxiliary inputs and the signals coming from the DAC. This allows to use an UAC 3552A-based USB speaker in a non-USB environment, like WIN 3.11 or other operating systems. On the other hand, it allows to connect additional analog sources, like CD-player or Walkman even while the speaker is connected to the USB. The input mixer is hardware-controlled by the AUXEN pin.
For external components, see section "Applications"
FOUTL
FOPL
FINL
UAC 3552A (Back-end)
Analog Vol. L
OUTL
-
from switch matrix
-
OUTR
-
-
Analog Vol. R
AVSS
VREF
AGNDC
FOUTR
FOPR
FINR
For external components, see section "Applications"
Fig. 2-2: Postfilter op amps and analog volume
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2.1.6. General Purpose I/O The GPIO pins are used to connect keys which are related to the USB HID class or for vendor-specific control functions and LEDs in order to indicate on/off states for example. The standard configuration defines the GPIOs as four input pins (GPIO0...GPIO3) and four output pins (GPIO4...GPIO7). The function of the input pins is shown in Table 2-2. Table 2-2: Standard Key Configuration Pin GPIO0 GPIO1 GPIO2 GPIO3 Function Volume Up Volume Down MuteToggle BassBoost Toggle Key Code 1 2 4 8 Usage ID E9 EA E2 E5
2.1.5.5. Analog Volume Control The analog volume control covers a range from 0 dB to -75 dB plus an additional mute position. The analog step size is split into a 3-dB and a 1.5-dB range:
-75 dB...-54 dB: -54 dB...0 dB:
3 dB step size 1.5 dB step size
The overall volume system, however, consists not only of the analog volume. An additional digital volume control allows a step size of 0.5 dB over the complete range. See Section 2.2.2.7. "Volume and Balance Control" on page 13. Please note that analog input signals (AUXL, AUXR) do not have the additional digital volume control.
2.1.5.6. Line-out/Headphone Amplifier The line-out/headphone amplifier output is provided at the OUTL and OUTR pins connected either to stereo headphones or to the power amplifier within an USB speaker. The stereo headphones require external 47- serial resistors in both channels. See Section 4. "Applications" on page 26.
The keys are polled by the microcontroller and the corresponding key codes are transmitted to the host on request. The relation between key code and usage ID (see Universal Bus HID Usage Tables, Version 1.0, Chapter 14 - Consumer Page) is defined in the HID report descriptor (see Section 2.2.1.4. "HID Report Descriptor" on page 11) which is transmitted to the host along with the configuration descriptor during the bus enumeration. When the device is not connected to USB, the functionality of the volume-control and mute pins are preserved. In this case, however, the parameters are directly transferred to the DSP-core. This allows using the device in stand-alone mode providing volume and mute control for analog sources. The output pins are not predefined and therefore not related to any USB functions. They can be set or reset by vendor-specific software. The standard configuration can be changed also by vendor-specific USB software, but in this case, Table 2-2 is no longer valid.
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2.1.7. Special I/O 2.1.7.1. SOF (Start of Frame) The SOF-pin provides a 1-ms signal which is synchronous to the USB 1-ms frame rate. It can be used for test purpose or as an USB-synchronous reference for vendor-specific external circuitry. 2.2. Software
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The functionality of the UAC 3552A is mainly defined by software. The internal -controller handles the USB requests whereas the Audio Processing Unit processes the sound features.
2.2.1. USB Microcontroller Software 2.1.7.2. AUXEN This is a digital input that has to be used if an analog signal is connected to the AUX R/L pins. It triggers the microcontroller to switch the input mixer to the analog input (the DAC signal always remains active!) and it keeps the device from entering the low-power mode which can be requested by the host PC or by disconnecting the device from the USB. 2.2.1.1. Chapter 9 Functions The chapter 9 of the USB Spec 1.1 defines the USB device framework which is the middle layer of the USB protocol hierarchy (see USB Spec 1.1 page 175). It handles routing data between the bus interface and various endpoints. The endpoint is a source or sink for data within the device.
2.2.1.2. Device Descriptor 2.1.7.3. SUSPEND The SUSPEND pin indicates the low-power mode. It can be used to power down external circuitry, like power amplifiers in an USB speaker. Table 2-3: SUSPEND pin SUSPEND low high normal power low power Unlike the configuration descriptor, which is located in ROM, the device descriptor is more flexible. The manufacturer-related data are stored in the on-chip EEPROM, and can be adapted individually. In detail these data are - vendor ID - product ID - device release number - manufacturer string - product string - serial number string A comfortable programming tool allows this data to be defined and writes it into the corresponding EEPROM location. The UAC 3552A is shipped with the Micronas device descriptor and allows USB functionality without any EEPROM reprogramming.
2.1.8. Clock System The UAC 3552A requires a 12-MHz clock source, which is realized as an on-chip oscillator with external crystal. Also an external oscillator can be used. In this case, the clock has to be connected to XTI. The 12 MHz is the input clock for a PLL circuit which generates all clocks needed within the IC.
2.2.1.3. String Descriptor The string descriptor is located in the EEPROM. The UAC 3552A holds three strings. The programming tool handles the programming of strings and will take care of string length control also. The UAC 3552A is shipped with the Micronas string descriptor and allows USB functionality without any EEPROM reprogramming.
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2.2.2.1. Sample Rate Converter The purpose of the sample rate converter is first to transform the block transferred audio data into a continuous data stream and second to convert all incoming sample rates to a fixed 50-kHz sample rate. This technique eliminates input data jitter. Furthermore, all audio algorithms and the DAC run on a single sample rate and no parameter switching is required on change of audio sampling rate. Furthermore, all audio clocks, such as sampling clock, noise-shaping clock, and DAC-clock can be derived from a single free-running 12-MHz oscillator. This mechanism allows continuous input sampling rates from 5 kHz up to 50 kHz.
2.2.1.4. HID Report Descriptor The HID report descriptor defines the functionality of the GPIO Pins. The basic information here are the usage IDs for the key inputs. These IDs are stored in the EEPROM and can therefore be modified if the default configuration does not fit the application. The UAC 3552A, however, only supports the default functions: volume up/down, mute on/off and BassBoost on/ off. This means, that all nonstandard usage IDs will be transmitted to the host on request and can be used with vendor specific software, but only the default IDs will work together with the operating system.
2.2.2. Audio Processing Software 2.2.2.2. Automatic Gain Control All audio processing is realized by DSP-software, apart from volume control which is located in the analog back-end. The audio building blocks split into USBindependent features, like sample rate conversion and oversampling filters and blocks which belong to the so called USB feature unit, defined in the USB Device Class Definition for Audio Devices. The feature unit provides basic manipulation of the incoming logical channels. The UAC 3552A supports two logical channels (i.e. left & right). Multichannel or surround systems, however, can also be realized using more than one UAC 3552A, because phase or delay distortion is eliminated by locking the audio processing to the USB frame rate. An overview of the architecture is given in Fig. 2-3. The Automatic Gain Control (AGC) is one of the building blocks of the feature unit (USB Device Class Definition for Audio Devices 1.0, page 39). Different sound sources fairly often do not have the same volume level. The Automatic Gain Control solves this problem by equalizing the volume levels within a defined range. Below a theshold level the signals are not affected. The level-adjustment is performed with time constants in order to avoid short-time adjustments due to signal peaks.
Feature Unit
Sample Rate Converter AGC Bass/Treble Bass Boost Equalizer Volume/ Balance OverSampling
Fig. 2-3: Audio processing
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2.2.2.3. Bass Control The bass control provides gain or attenuation to frequency components below a corner frequency of 120 Hz. The characteristic is shown in Fig. 2-4. 2.2.2.4. Treble Control
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The treble control provides gain or attenuation to frequency components above a corner frequency of 6 kHz. The characteristic is shown in Fig. 2-5.
dB
15
dB
15
10
10
5
5
0
0
-5
-5
-10
-10
-15
-15
10. 50. 100. 500. 1000. 5000. 10000.
10.
50.
100.
500.
1000.
5000.
10000.
Hz
Hz
Fig. 2-4: Bass control
Fig. 2-5: Treble control
The bass control works identically on both channels. Table 2-4: Bass Control Characteristics Min Max +12 dB Step 0.5 dB
The treble control works identically on both channels. Table 2-5: Treble Control Characteristics Min Max +12 dB Step 0.5 dB
-12 dB
-12 dB
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2.2.2.7. Volume and Balance Control The volume and balance control operate separately on the left and right channel. Table 2-7: Volume and Balance Control
2.2.2.5. Bass Boost Control The bass boost algorithm provides an additional 12-dB gain for the low-frequency components. The characteristic is shown in Fig. 2-6.
dB
14 12
Min
Max 0 dB
Step 0.5 dB
-75 dB
10 8 6 4
2 0
10.
20.
50.
100.
200.
500.
1000.
Hz
The volume control is realized in the analog back-end. This preserves high audio quality (SNR) at low volume settings because signal and noise are attenuated in the same way, which is not the case for pure digital volume control. The UAC 3552A uses digital volume control only for the fine tuning of the 0.5 dB step size. The volume setting is smoothed by an internal ramping algorithm in order to avoid audible clicks during volume change. The splitting between analog and digital volume is handled by the UAC 3552A automatically.
Fig. 2-6: Bass boost
The bass boost works on both channels and can be switched on and off under USB control. 2.2.3. Mute Control 2.2.2.6. Parametric Equalizer The parametric equalizer is a non-USB audio feature. It allows the compensation of unwanted frequency responses of a speaker. Alternatively, frequency responses can be set to suit individual tastes. The equalizer consists of 5 individually adjustable bands. The control parameters and the parameter range for each band is shown in Table 2-6. Table 2-6: Equalizer Parameters Parameter center frequency gain/attenuation filter quality (Q) Min 50 Hz Max 15 kHz
dB
The mute control is part of the volume system in the UAC 3552A. It functions simultaneously on both channels and can be switched on and off under USB control. As with the volume control, clicks are avoided by a ramping algorithm.
2.2.3.1. Oversampling The oversampling filter increases the audio sampling rate by a factor of 4. The final upsampling to the noiseshaping rate is handled by a sample and hold circuit. The pass-band characteristic of the oversampling filter is shown in Fig. 2-7.
-6 dB
0.5
+6 dB 3
0
-0.1
-0.2
The adjustment of the equalizer is supported by an application program that allows to set up frequency responses and to download the corresponding filter coefficients into the UAC 3552A. When the frequency response fits the target, it can be programmed into the on-chip EEPROM. The UAC 3552A is shipped with a flat frequency response.
-0.3
-0.4
-0.5 0 5000 10000 15000 20000
kHz
Fig. 2-7: 1 to 4 Oversampling filter, pass-band
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3. Specifications 3.1. Outline Dimensions
10 x 0.8 = 8 0.1 0.17 0.06 33 34 13.2 0.2 23 22 10 0.1 0.8 0.8
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1.3 12 1 1.75 13.2 0.2 2.15 0.2 11
1.75
44
2.0 0.1 0.1 10 0.1
0.375 0.075
SPGS0006-3(P44)/1E
Fig. 3-1: 44-Pin Plastic Metric Quad Flat Pack (PMQFP44) Weight approximately 0.4 g Dimensions in mm
3.2. Pin Connections and Short Descriptions NC = not connected, leave vacant LV = if not used, leave vacant VSS = if not used, connect to VSS Pin No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Pin Name AGNDC AVSS1 AVSS0 OUTL OUTR AVDD0 AVDD1 XTI XTO NC NC NC NC GPIO 0 GPIO 1 IN IN Type IN/OUT IN IN OUT OUT IN IN IN OUT = obligatory; connect as described in circuit diagram VDD = connect to VDD Connection
(If not used)
X
Short Description Analog reference voltage VSS 1 for audio back-end VSS 0 for audio output amplifiers Audio Output: Headphone left or Speaker + Audio Output: Headphone right or Speaker - VDD 0 for audio output amplifiers VDD 1 for audio back-end quartz oscillator pin 1 quartz oscillator pin 2 Not connected Not connected Not connected Not connected HID IO 0 HID IO 1
X X X LV LV X X X X LV LV LV LV VSS VSS
14
10 x 0.8 = 8 0.1
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Pin No. 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44
Pin Name GPIO 2 GPIO 3 NC GPIO 4 GPIO 5 GPIO 6 GPIO 7 TRDY DMINUS DPLUS VREG VDD VSS TEST RESQ SUSPEND SOF AUXEN NC NC AUXL AUXR FOUTL FOPL FINL FOUTR FOPR FINR VREF
Type IN IN
Connection
(If not used)
Short Description HID IO 2 HID IO 3 Not connected HID IO 4 HID IO 5 HID IO 6 HID IO 7 Test Output Pin USB DATA MINUS USB DATA PLUS Capacitor for internal supply digital VDD digital VSS Test Enable Power On Reset, active low Low-Power Mode Indicator 1-ms Start-Of-Frame Signal Enable AUX Input Not connected Not connected AUX Input Left AUX Input Right Output to left external filter Filter op amp inverting input, left Input for FiltoutL or filter op amp output (line out) Output to right filter op amp Right Filter op amp inverting input Input for FILTOUTR or Filter op amp output (line out) Analog reference Ground
VSS VSS LV
OUT OUT OUT OUT OUT IN/OUT IN/OUT OUT IN IN IN IN OUT OUT IN
LV LV LV LV LV X X X X X X VDD LV LV VSS LV LV
IN IN OUT IN/OUT IN/OUT OUT IN/OUT IN/OUT IN
VSS VSS X X X X X X X
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3.3. Pin Descriptions 3.3.1. Power Supply Pins The UAC 3552A combines various analog and digital functions which may be used in different modes. For optimized performance, major parts have their own power supply pins. All VSS power supply pins must be connected. VDD (27) VSS (28) The VDD and VSS power supply pair are connected internally with all digital parts of the UAC 3552A. AVDD0 (6) AVSS0 (3) AVDD0 and AVSS0 are separate power supply pins that are exclusively used for the on-chip headphone/ loudspeaker amplifiers. AVDD1 (7) AVSS1 (2) The AVDD1 and AVSS1 pins supply the analog audio processing parts, except the headphone/loudspeaker amplifiers.
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AUXL (36) AUXR (37) The AUX pins provide two analog stereo inputs. Auxiliary input signals, e.g. the output of a conventional receiver circuit or the output of a tape recorder can be connected with these inputs. The input signals have to be connected by capacitive coupling. FOUTL (38) FOPL (39) FINL (40) FOUTR (41) FOPR (42) FINR (43) Filter op amps are provided in the analog baseband signal paths. These inverting op amps are freely accessible for external use by these pins. The FOUTL/R pins are connected with the buffered output of the internal switch matrix. The FOPL/R-pins are directly connected with the inputs of the inverting filter op amps. The FINL/R pins are connected with the outputs of the op amps. OUTL (4) OUTR (5) The OUTL/R pins are connected to the internal output amplifiers. They can be used for either line-out or stereo headphones. Caution: A short circuit at these pins for more than a momentary period may result in destruction of the internal circuits. XTI (8) XTO (9) The XTI pin is connected to the input of the internal crystal oscillator; the XTO pin to its output. Both pins should be directly connected to the crystal and two ground-connected capacitors (see application diagram).
3.3.2. Analog Audio Pins AGNDC (1) Reference for analog audio signals. This pin is used as reference for the internal op amps. This pin must be blocked against VREF with a 3.3-F capacitor. Note: The pin has a typical DC-level of 2.25 V. It can be used as reference input for external op amps when no current load is applied. VREF (44) Reference ground for the internal band-gap and biasing circuits. This pin should be connected to a clean ground potential. Any external distortions on this pin will affect the analog performance of the UAC 3552A. DMINUS (24) DPLUS (25) Differential USB port pins.
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3.4. Pin Configuration
VSS TEST RESQ VDD VREG DPLUS DMINUS TRDY
3.3.3. Other Pins TEST (29) Test enable. This pin is for test purposes only and must always be connected to VSS. VREG (26) This pin is used to connect an external buffer capacitor to stabilize the internal supply for the USB transceiver. RESQ (30) This pin may be used to reset the chip. GPIO 0 ... GPIO 7 (14,15,16,17,19,20,21,22) These pins are configurable to be either input or output and can be used to connect audio function keys or signalling LEDs. SUSPEND (31) This pin indicates that the host PC sets the USB bus to the suspend-mode state. SOF(32) Start of Frame Signal. 1-ms signal that can be used for external application circuits. AUXEN (33) Aux enable. This pin must be connected to VSS if an analog source is connected to the AUX input. Otherwise connect to VDD. TRDY (23) Test Output Pin. This pin is intended for test purposes only and must not be connected.
SUSPEND SOF AUXEN
33 32 31 30 29 28 27 26 25 24 23 NC NC AUXL AUXR FOUTL FOPL FINL FOUTR FOPR FINR VREF 34 35 36 37 38 39 40 41 42 43 44 1 AGNDC AVSS1 AVSS0 OUTL OUTR AVDD0 XTI AVDD1 NC XTO 2 3 4 5 6 7 8 9 10 11 NC 22 21 20 19 18 GPIO 7 GPIO 6 GPIO 5 GPIO 4 NC GPIO 3 GPIO 2 GPIO 1 GPIO 0 NC NC
UAC 3552A
17 16 15 14 13 12
Fig. 3-2: 44-pin PMQFP package
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3.5. Pin Circuits
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ext. filter network FOUTn FOPn FINn
AUXL/R
AGNDC Fig. 3-8: Input Pins AUXL/R AGNDC Fig. 3-3: Pins FINR, FOPR, FINL, FOPL AGNDC AGNDC
125 k
OUTn
Fig. 3-9: Output Pins OUTL, OUTR
VREF AVSS0/1 Fig. 3-4: Pins AGNDC, VREF
DVSUP P N GND Fig. 3-10: Digital Output Pins SOF, SUSPEND
FOUTn DPLUS AGNDC Fig. 3-5: Output Pins FOUTL, FOUTR
DMINUS
XTO
500 k
XTI Fig. 3-6: Output/Input Pins XTI, XTO
Fig. 3-11: Digital Input/Output Pins DMINUS, DPLUS
DVSUP P N GND Fig. 3-12: Input/Output Pins GPIO0...GPIO7
Fig. 3-7: Input Pins RESQ, TEST, AUXEN
18
Micronas
PRELIMINARY DATA SHEET
UAC 3552A
3.6. Electrical Characteristics 3.6.1. Absolute Maximum Ratings Symbol TA TS PPmax VSUPA VSUPD VIdig IIdig IIdig IOdig VIana IIana IOaudio
1) 2)
Parameter Ambient Operating Temperature Storage Temperature Power Dissipation Analog Supply Voltage1) Digital Supply Voltage Input Voltage, all digital inputs Input Current, all digital inputs Input Current, all digital outputs Output Current, all digital outputs Input Voltage, all analog inputs Input Current, all analog inputs Output Current, audio output2)
Pin Name
Min. 0
Max. 70 125 900 6 6 VSUPD + 0.3 +0.5 8 14.8 VSUPA + 0.3
Unit
C C
mW V V V mA mA mA V mA A
-40 -
AVDD0/1
-0.3 -0.3 -0.3 -5 -8 -14.8 -0.3 -5
-5
0.2
OUTL/R
Both have to be connected together! These pins are NOT short-circuit proof!
Stresses beyond those listed in the "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only. Functional operation of the device at these or any other conditions beyond those indicated in the "Recommended Operating Conditions/Characteristics" of this specification is not implied. Exposure to absolute maximum ratings conditions for extended periods may affect device reliability.
Micronas
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UAC 3552A
3.6.2. Recommended Operating Conditions Symbol Parameter Pin Name Min.
PRELIMINARY DATA SHEET
Typ.
Max.
Unit
Temperature Ranges and Supply Voltages TA VSUPA1 VSUPD Ambient Temperature Range Analog Audio Supply Voltage Digital Supply Voltage AVDD0/1 VDD 0 4.5 4.5 5.0 5.0 70 5.5 5.5
C
V V
Relative Supply Voltages VSUPA Analog Audio Supply Voltage in relation to the Digital Supply Voltage Input Voltage Low Input Voltage high Reset Input high-low transition voltage Reset Input low-high transition voltage Reset low time after VDD stable and oscillator start-up AVDD0/1 VSUPD -0.25 V 5.5 V
VIL VIH VRIL VRIH TRL
GPI[7:0], AUXEN, GPI[7:0], AUXEN RESQ RESQ RESQ 0.8 5 0.75
0.25
VSUPD VSUPD
0.45
VSUPD VSUPD
s
Analog Reference CAGNDC1 CAGNDC2 Analog Reference Capacitor Analog Reference Capacitor AGNDC AGNDC 1.0 3.3 10
F
nF
Analog Audio Inputs VAI Analog Input Voltage AC AUXL/R 0.525 1.05 Vrms
Analog Filter Input and Output ZAFLO ZAFLI Analog Filter Load Output1) Analog Filter Load Input1) FOUTL/R FINL/R 7.5 6 5.0 7.5 Analog Audio Output ZAOL_HP Analog Output Load HP (47 Series Resistor required) OUTL/R 32 400 k pF k pF
pF
20
Micronas
PRELIMINARY DATA SHEET
UAC 3552A
Symbol
Parameter
Pin Name
Min.
Typ.
Max.
Unit
Quartz Characteristics TAC FP Ambient Temperature Range Load Resonance Frequency at Cl = 20 pF Accuracy of Adjustment Frequency Variation versus Temperature Equivalent Series Resistance Shunt (parallel) Capacitance 0 12 70
C
MHz
F/Fs F/Fs
REQ C0
-20 -20
12 3
20 20 30 5
ppm ppm
pF
Voltage Regulator CVREG1 CVREG2 Transceiver RUSB CUSB
1)
Voltage Regulator Capacitor Voltage Regulator Capacitor
VREG VREG
1.0
3.3 10
F
nF
Input Serial Resistance Shunt Capacitor
DPLUS/ DMINUS DPLUS/ DMINUS
24 (0.5 %) 22
pF
Please refer to Section 4.1. "Recommended Low-Pass Filters for Analog Outputs" on page 26.
Micronas
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UAC 3552A
3.6.3. Characteristics
PRELIMINARY DATA SHEET
At TA = 0 to 70 C, VSUPD = 4.75 V to 5.25 V, VSUPA = 4.75 V to 5.25 V; typical values at TJ = 27 C, VSUPD = VSUPA = 5.0 V, quartz frequency = 12 MHz, duty cycle = 50 %, positive current flows into the IC bass/treble: 0 dB, bass boost: off, AGC: off, equalizer: off
Symbol Parameter Pin Name Min. Typ. Max. Unit Test Conditions
Digital Supply IVDD Current Consumption1) VDD 100 125.5 mA VSUPD =5 V
Digital Input Pin - Leakage II Input Leakage Current GPIO[7:0], AUXEN, RESQ
1
A
VGND VI VSUP
Digital Output Pin VOH VOL Output High Voltage Output Low Voltage GPIO[7:0], SUSPEND, SOF VSUPD - 0.4 0.4 V V Iout =8 mA
Analog Supply IAVDD PSRRAA Current Consumption Analog Audio Power Supply Rejection Ratio for Analog Audio Output AVDD0/1, OUTL/R 11 2 50 20 Reference Frequency Generation VDCXTI CLI CLO VXTALOUT DC Voltage at Oscillator Pins Input Capacitance at Oscillator Pin Input Capacitance at Oscillator Pin Voltage Swing at Oscillator Pins (peak-peak) Oscillator Start-Up Time EEPROM EEPROM unpowered data retention Number of write cycles
1)
15
mA mA dB dB
SUSPD = 0, Mute SUSPD = 1, Mute 1 kHz sine at 100 mVrms 100 kHz sine at 100 mVrms
XTI/O XTI XTO XTI/O 0.6 * VSUPA
0.5 * VSUPA 3 3 1.0 * VSUPA 10
V pF pF V ms
10 100
year
no load attached to GPIO's
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Micronas
PRELIMINARY DATA SHEET
UAC 3552A
Symbol
Parameter
Pin Name
Min.
Typ.
Max.
Unit
Test Conditions
USB Transceiver VREG RO Regulator Voltage Driver Output Resistance including the 24- external serial resistor Rise and Fall Times Rise/Fall Time Matching Crossover Voltage Differential Receiver Common-Mode Range Single-ended Receiver Threshold Voltage VREG DPLUS/ DMINUS DPLUS/ DMINUS DPLUS/ DMINUS DPLUS/ DMINUS DPLUS/ DMINUS DPLUS/ DMINUS 3.25 28 3.4 3.55 43 V CL=1F static, LOW or HIGH
tr / tf MA_TRTF VXOVER VCM_DREC VT_SREC
4 90 1.3 0.8 0.8
20 111.1 2.0 2.5 2.0
ns % V V V
CL=50 pF, driver mode CL=50 pF, driver mode CL=50 pF, driver mode
Analog Audio VAGNDC RIAUX Analog Reference Voltage Input Resistance at Input Pins AGNDC AUXL/R 12.1 11.6 2.25 15 17.9 19.0 V k k RL >> 10 M, referred to VREF TJ = 27 C TA = 0 to 70 C Input selected, SUSPD = 0 i = 10 A, referred to VREF TJ = 27 C TA = 0 to 70 C Input not selected SUSPD = 1 i = 10 A, referred to VREF TJ = 27 C SUSPD = 1 i = 200 A, referred to VREF SUSPD = 1, Mute i = 10 A, referred to VREF SUSPD = 0, referred to AGNDC SUSPD = 0, Mute referred to AGNDC SUSPD = 0, referred to AGNDC SUSPD = 0, referred to AGNDC Analog Gain = Mute, SUSPD switched from 0 to 1
24.2 23.3
30
35.8 37.9
k k
ROOUT
Output Resistance at Output Pins
OUTL/R
700
ROFILT
Output Resistance of Filter Pins Offset Voltage at Input Pins Offset Voltage at Output Pins Offset Voltage at Filter Output Pins Offset Voltage at Filter Input Pins Difference of DC Voltage at Output Pins after Back-end Low Power Sequence
FINL FINR
15 11.25
k k 20 10 20 20 10 mV mV mV mV mV
VOffI VOffO VOffFI VOffFO dVDCPD
AUXL/R OUTL/R FOUTL/R FINL/R OUTL/R
-20 -10 -20 -20 -10
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UAC 3552A
PRELIMINARY DATA SHEET
Symbol RD/A
Parameter D/A Pass Band Ripple
Pin Name OUTL/R, FOUTL/R
Min.
Typ. 0.01
Max.
Unit dB
Test Conditions 0...22 kHz (no external filters used) 31 kHz...164 kHz (no external filters used)
AD/A
D/A Stop Band Attenuation
60
dB
BWAUX THDHP
Bandwidth for Auxiliary Inputs Total Harmonic Distortion
AUXL/R, FINL/R OUTL/R
760 0.05
kHz % BW = 20 Hz...0.5 fs, unweighted, RL 32 (47 series resistor required), Analog Gain = 0 dB, Input 1 kHz at -3 dBFS input -40 dB below 1.05 Vrms RL 32 (external 47 series resistor required) BW =20 Hz...0.5 fs unweighted, Analog Gain = 0 dB, Input = -20 dBFS RL 32 (external 47 series resistor required) BW = 20 Hz..0.5 fs unweighted Analog Gain= -40.5 dB, Input = -3 dBFS BW = 20 Hz...22 kHz unweighted, no digital input signal, Analog Gain = Mute RL > 5 k, Analog Gain = 0 dB Input = 0 dBFS digital f = 1 kHz, sine wave, RL > 5 k 0.5 Vrms to AUXL/R RL = 32 , Analog Gain = +2 dB, distortion < 1%, external 47 series resistor required
SNRAUX
Signal-to-Noise Ratio from Analog Input to Outputs Signal-to-Noise Ratio
AUXn, OUTL/R OUTL/R 89
96
dB
SNR1
91
dB
SNR2
Signal-to-Noise Ratio
OUTL/R
58
62
dB
LevMute
Mute Level
OUTL/R
-110
dBV
VAO
Analog Output Voltage AC
OUTL/R
1.0
1.05
1.1
Vrms
GAUX
Gain from Auxiliary Inputs to Outputs Output Power (Headphone)
AUXL/R, OUTL/R OUTL/R
-0.5
0
0.5
dB
PHP
12
mW
24
Micronas
PRELIMINARY DATA SHEET
UAC 3552A
Symbol GAO dGAO1 dGAO2 EGA1 EGA2 EGA3 EdGA XTALKHP
Parameter Analog Output Gain Setting Range Analog Output Gain Step Size Analog Output Gain Step Size Analog Output Gain Error Analog Output Gain Error Analog Output Gain Error Analog Output Gain Step Size Error Crosstalk Left/Right Channel (Headphone)
Pin Name OUTL/R OUTL/R OUTL/R OUTL/R OUTL/R OUTL/R OUTL/R OUTL/R
Min.
Typ.
Max. 18
Unit dB dB dB
Test Conditions
-75
3.0 1.5
-75 dB...-54 dB -54 dB...+18 dB
Analog Gain = -54 dB Analog Gain = -45 dB Analog Gain = -39 dB Analog Gain = -48 dB f = 1 kHz, sine wave, OUTL/R: RL 32 (47 series resistor required) Analog Gain = 0 dB, Input = -3 dBFS or 0.7 Vrms to AUXL/R f = 1 kHz, sine wave, FOUTL/R: RL > 7.5 k OUTL/R: RL 32 (47- series resistor required) Analog Gain = 0 dB, Input = -3 dBFS and 0.7 Vrms to AUXL/R Analog Gain:
Analog Gain:
-2 -1 -0.5 -0.5 -70 -80
2 1 0.5 0.5
dB dB dB dB dB
XTALK2
Crosstalk between Input Signal Pairs
AUXnL/R
-70
-80
dB
Micronas
25
UAC 3552A
4. Applications
3rd-order
PRELIMINARY DATA SHEET
4.1. Recommended Low-Pass Filters for Analog Outputs 1)
1st-order
15 k 330 pF 15 k FOUTL(R)
15 k 7.5 k 7.5 k 120 pF
7.5 k
1.8 nF
AVSS
1.8 nF
FOPL(R)
FINL(R)
-
FOUTL(R) FOPL(R) FINL(R)
-
Fig. 4-3: 3rd-order low-pass filter Fig. 4-1: 1st-order low-pass filter Table 4-1: Attenuation of 1st-order low-pass filter Frequency 24 kHz 30 kHz Gain Table 4-3: Attenuation of 3rd-order low-pass filter Frequency 18 kHz 24 kHz 30 kHz Gain 0.17 dB
-2.2 dB -3.0 dB
-0.23 dB -3.00 dB
2nd-order
11 k 11 k
11 k 220 pF
1.0 nF
AVSS
FOUTL(R)
FOPL(R)
FINL(R)
-
Fig. 4-2: 2nd-order low-pass filter Table 4-2: Attenuation of 2nd-order low-pass filter Frequency 24 kHz 30 kHz Gain
-1.5 dB -3.0 dB
1)
without deemphasis circuit
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Micronas
R 1 11k Volume up R 3 11k C1 Volume down R5 D1 R7 C3 Mute 11k R 1 0 11k D2 R12 R 1 3 1k D3 R 1 5 1k D4 LED LED C4 220p 11k R14 11k C5 220p LED R 1 1 11k Bass Boost S4 R9 11k 1n R8 1k LED 11k R 6 11k S3 1n R4 S2 1k
35 34 18 13 12 11 10
U1 NC6 NC5 NC4 NC3 NC2 NC1 NC0 FinR Fo p R FoutR FinL FopL FoutL
43 42 41 40 39 38
1 5 4 3 2 C6 36 37 AU X L AU X R C8 OUTR OUTL + UAC 3 5 5 2 A C10 + 5 4 + d m i nu s dplus 2 3 6 7 8 9 26 27 28 44 1 C7 AV S S 1 AV S S 0 AV D D 0 AV D D 1 XTI XTO VREG VDD VSS VREF AGNDC R21 11k 24 25 470n 470n 160u/16V C9 160u/16V
1
VREG
J15 C11 C16 100n 470n Y1 1 J16 D+ 1
22p
R25 1.5k
J14 D-
R 2 6 24 0.5%
VREG
DD+
3.3u/16V C14 10n 5Vdig
1 2 3 4
R 2 8 680 J18 RCA right
R27
24 0.5% 12MHz C17 22p 5Vdig VO U T C19 100n R 2 9 single connection point 100n C20 2 L1 Ferrite bead 5Vana + C21 47u/16V C18 22p
22p C16 100n
USB ser ies B
U2 LM7805
P1
1
VIN
8VDC
D5 1n4001
+
C23
100n
UAC 3552A
47u/16V
3
C22
GND
1
Micronas
S1 5Vdig J7 GPIO7 GPIO6 GPIO5 GPIO4 22 21 20 19 GPIO7 GPIO6 GPIO5 GPIO4 GPIO0 GPIO1 GPIO2 GPIO3 GPIO0 GPIO1 GPIO2 GPIO3 R 1 7 1k test resq TEST RES# AU X E N auxen 29 30 33 14 15 16 17 2 3 4 5 1 P H O N E J AC K S T E R E O S W R19 1k R 2 0 47
5Vdig
R2
220k
4.2. Typical Application
resq
Fig. 4-4: Application circuit
PRELIMINARY DATA SHEET
C2
470n
5Vdig
R16 150k
J11
R18 11k
UAC 3552A
SOF Suspend T R DY
32 31 23
P H O N E J AC K S T E R E O S W 5Vana
R 2 2 47 R23 1k R 2 4 680
J12 left
J13 RCA left
J17 right
27
UAC 3552A
5. Data Sheet History 1. Preliminary data sheet: "UAC 3552A Universal Serial Bus DAC, Nov. 9, 1999, 6251-487-1PD. First release of the preliminary data sheet.
PRELIMINARY DATA SHEET
Micronas GmbH Hans-Bunte-Strasse 19 D-79108 Freiburg (Germany) P.O. Box 840 D-79008 Freiburg (Germany) Tel. +49-761-517-0 Fax +49-761-517-2174 E-mail: docservice@micronas.com Internet: www.micronas.com Printed in Germany Order No. 6251-487-1PD
All information and data contained in this data sheet are without any commitment, are not to be considered as an offer for conclusion of a contract, nor shall they be construed as to create any liability. Any new issue of this data sheet invalidates previous issues. Product availability and delivery are exclusively subject to our respective order confirmation form; the same applies to orders based on development samples delivered. By this publication, Micronas GmbH does not assume responsibility for patent infringements or other rights of third parties which may result from its use. Further, Micronas GmbH reserves the right to revise this publication and to make changes to its content, at any time, without obligation to notify any person or entity of such revisions or changes. No part of this publication may be reproduced, photocopied, stored on a retrieval system, or transmitted without the express written consent of Micronas GmbH.
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Micronas

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